Semiconductor processing method

ABSTRACT

In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. In yet another implementation, a transistor comprises a semiconductive substrate and a gate stack formed thereover. The stack in at least one cross section defines a channel length within the substrate of less than 1 micron, with the stack comprising conductive material formed over a gate dielectric layer. An insulative layer is formed on outer lateral edges of the conductive material, with such layer having opposing substantially continuous straight linear outer lateral edges over all conductive material of the gate stack within the one cross section.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods,including methods of fabricating electronic components such astransistors.

BACKGROUND OF THE INVENTION

[0002] Field effect transistors are comprised of a pair of diffusionregions, referred to as a source and a drain, spaced apart within asemiconductive substrate. The transistors include a gate providedadjacent a substrate separation region between the diffusion regions forimparting an electric field to enable current to flow between thediffusion regions. The substrate material adjacent the gate and betweenthe diffusion regions is referred to as the channel.

[0003] The semiconductive substrate typically comprises bulk crystallinesilicon having a light conductivity doping impurity concentration ofopposite type to the predominate doping of the source and drain regions.Alternately, the substrate can be provided in the form of a thin layerof lightly doped semiconductive material over an underlaying insulatinglayer. Such are commonly referred to as semiconductor-on-insulator (SOI)constructions. In the context of this document, the term “semiconductivesubstrate” is defined to mean any construction comprising semiconductivematerial, including, but not limited to, bulk semiconductive materialssuch as a semiconductive wafer (either alone or in assemblies comprisingother materials thereon), and semiconductive material layers (eitheralone or in assemblies comprising other materials). The term “substrate”refers to any supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0004] Integrated circuitry fabrication technology continues to striveto increase circuit density, and thereby minimize the size and channellengths of field effect transistors. Improvements in technology haveresulted in reduction of field effect transistor size from long-channeldevices (i.e., channel lengths greater than two microns), toshort-channel devices (i.e., channel lengths less than two microns), andto sub-micron devices (i.e., channel lengths less than one micron). Asfield effect transistor channel lengths (i.e., gate or word line widths)became smaller than two microns, so-called short-channel effects beganto become increasingly significant. As a result, device design andconsequently process technology had to be modified to take these effectsinto account so that optimum device performance could continue to beobtained. For example, the lateral electrical field in the channelregion increases as a result of smaller transistor channel lengths asthe supply voltage remains constant. If the field becomes strong enough,it can give rise to so-called hot-carrier effects. Hot-carrier effectsoften lead to gate oxide degradation, as energetic carriers can beinjected into gate oxide and become permanent charges.

[0005] Two recognized solutions to this problem, used either alone or incombination, include source/drain re-oxidation and provision of lightlydoped drain (LDD) regions. Source/drain re-oxidation effectively grows alayer of thermal oxide over the source and drain areas as well as overthe gate sidewalls. The oxidation has the effect of rounding the polygate edge corners in effectively oxidizing a portion of the gate andunderlying substrate, thereby increasing the thickness of the gate oxidelayer at least at the edges of the gate. Such reduces the gate-to-drainoverlap capacitance, and strengthens the gate oxide of the polysilicongate edge. The latter benefits are effectively obtained becauseoxidation-induced encroachment gives rise to a graded gate oxide underthe polysilicon edge. The thicker oxide at the gate edge relieves theelectric-field intensity at the corner of the gate structure, thusreducing short-channel effects.

[0006] An example technique for accomplishing such re-oxidation includesconventional wet and dry oxidations at atmospheric pressure and at atemperature of 800° C. or greater. Typical process exposure time is 10minutes, which also grows a layer of oxide from 50 to 200 Angstromsthick on the sidewalls of the patterned gate.

[0007] LDD regions are provided within the substrate relative to thechannel region in advance of the source and drains, and further reducehot-carrier effects. The LDD regions are provided to be lighterconductively doped (i.e., less concentration) than the source and drainregions. This facilitates sharing the voltage drop between the drain andthe channel, as opposed to the stark voltage drop at the channeloccurring in non-LDD transistors. The LDD regions absorb some of thevoltage drop potential into the drain, thus effectively eliminatinghot-carrier effects. As a result, the stability of the device isincreased.

[0008] Most commonly, a combination of source/drain re-oxidation andformation of LDD regions is utilized. However in combination, theseprocesses can create problems, particularly in fabrication of sub-microndevices.

[0009] For example, consider FIGS. 1-2. FIG. 1 depicts a semiconductorwafer fragment 10 comprised of a bulk monocrystalline substrate 12having a gate structure 14 formed thereover. Gate 14 comprises a gateoxide layer 16, an overlying conductively doped polysilicon layer 18, anoverlying refractory metal silicide layer 20, and an insulative cap 22,such as Si₃N₄. That region beneath gate oxide layer 16 within bulksubstrate 12 will constitute the channel region of the resultanttransistor. Unfortunately when subjected to source/drain re-oxidation,the differing materials of gate 14 do not oxidize at the same rate. FIG.2 illustrates an oxide layer 24 formed over substrate 12 and thesidewalls of gate structure 14 after a source/drain re-oxidation.Silicide layer 20 of gate structure 14 has a tendency to oxidize at asignificantly greater rate than the oxidation of either nitride layer 22or polysilicon layer 18. Such results in the formation of theillustrated sidewall bulges 25.

[0010] The typical manner by which LDD regions are fabricated is by ionimplantation of conductivity dopant impurity after source/drainre-oxidation, such as regions 26. Unfortunately, oxide bulges 25 inlayer 24 effectively function as a mask to such ion implantation. Thisresults in formation of LDD implant regions 26 being laterally spacedoutwardly away from the original sidewalls of gate structure 14. This isundesirable. More preferably, the inner lateral edges of LDD regions 26are desirably as close to the gate edges as possible.

[0011] The invention was principally motivated in overcoming drawbackssuch as that described above with respect to field effective transistorsfabrication. The artisan will, however, appreciate applicability of thefollowing invention to other aspects of semiconductor wafer processingin formation of other electronic components or devices, with theinvention only being limited by the accompanying claims appropriatelyinterpreted in accordance with the Doctrine of Equivalents.

SUMMARY OF THE INVENTION

[0012] The invention comprises semiconductor processing methods, methodsof forming electronic components, and transistors. In oneimplementation, first and second layers are formed over a substrate. Oneof the layers has a higher oxidation rate than the other when exposed toan oxidizing atmosphere. The substrate has a periphery. The layers,respectively, have an exposed outer edge spaced inside the substrateperiphery. Etching is conducted into the higher oxidation rate materialat a faster rate than any etching which occurs into the lower oxidationrate material. After the etching, the substrate is exposed to theoxidizing atmosphere.

[0013] In but one other implementation, a stack of at least twoconductive layers for an electronic component is formed over asubstrate. The two conductive layers have different oxidation rates whenexposed to an oxidizing atmosphere. The layer with the higher oxidationrate has an outer lateral edge which is recessed inwardly of acorresponding outer lateral edge of the layer with the lower oxidationrate. The stack of conductive layers is exposed to the oxidizingatmosphere effective to grow an oxide layer over the outer lateral edgesof the first and second layers.

[0014] In but one other implementation, a transistor comprises asemiconductive substrate and a gate stack formed thereover. The gatestack in at least one cross section defines a channel length within thesemiconductive substrate of less than 1 micron, with the gate stackcomprising conductive material formed over a gate dielectric layer. Aninsulative layer is formed on outer lateral edges of the conductivematerial, with the insulative layer having opposing substantiallycontinuous straight linear outer lateral edges over all conductivematerial of the gate stack within the one cross section.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0016]FIG. 1 is a diagrammatic sectional view of a prior artsemiconductor wafer fragment at a prior art processing step, and isdescribed in the “Background” section above.

[0017]FIG. 2 is a view of the FIG. 1 wafer fragment at a prior artprocessing step subsequent to that show by FIG. 1.

[0018]FIG. 3 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with the invention.

[0019]FIG. 4 is a view of the FIG. 3 wafer fragment at a processing stepsubsequent to that shown by FIG. 3.

[0020]FIG. 5 is a view of the FIG. 3 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0021]FIG. 6 is a view of the FIG. 3 wafer fragment at a processing stepsubsequent to that shown by FIG. 5.

[0022]FIG. 7 is a view of the FIG. 3 wafer fragment at a processing stepsubsequent to that shown by FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0024] Referring initially to FIG. 3, a semiconductor wafer fragment 30comprises a bulk monocrystalline silicon substrate 32. A gate dielectriclayer 33 (i.e., SiO₂), a conductively doped silicon layer 34 (i.e.,polysilicon), a silicide layer 35 (i.e., a refractory metal silicide,such as WSi_(x)) and an insulating layer 36 (i.e., doped or undopedSiO₂, Si₃N₄, etc.) are formed over monocrystalline substrate 32.Silicide layer 35 has a higher oxidation rate than oxidation rates oflayers 34 and 36 when exposed to an oxidizing atmosphere, with anexample oxidizing atmosphere being oxygen gas at a temperature of about950° C.

[0025] Referring to FIG. 4, insulating layer 36, silicide layer 35,doped silicon layer 34, and gate dielectric layer 33 are patterned andetched (i.e., by photolithography) to form a conductive gate stack 38(having an insulating cap 39) over a channel region 40 of substrate 32.The preferred technique for forming the illustrated stack is by dryetching, for example, using chemistries comprising CH₄/CHF₃ for theinsulative cap, NF₃/Cl₂ for the silicide, and Cl₂/HBr for thepolysilicon. Gate stack 38 comprises two opposing and respectivelylinearly aligned outer lateral edges 42 and 44 of the insulatingsilicide and doped silicon layers. Accordingly or alternatelyconsidered, layers 34 and 35 constitute first and second layers (bothbeing conductive in this example) formed over a substrate, with thesecond layer being formed over the first and having a higher oxidationrate than the first when exposed to a certain oxidizing atmosphere.Although layer 35 is shown received over layer 34, the relationshipmight be reversed depending on the processor's desire and the componentbeing fabricated. The first and second conductive materials in thisexample have been etched to form a conductive component, here in theform of a transistor gate 38. The substrate has a periphery (outside ofthe cross-sectional views of FIGS. 3-7), with first layer 34 having anexposed first outer edge (i.e., so either edge 42 or 44) spaced insidethe substrate periphery, and with second layer 35 having an exposedfirst outer edge (i.e., either edge 42 or 44) spaced inside thesubstrate periphery.

[0026] Layer 36 (cap 39) comprises a third layer formed over the firstand second layers, with itself having an exposed outer edge (i.e.,either edge 42 or 44) spaced inside the substrate periphery. Third layer36 has a lower oxidation rate than the oxidation rate of second layer 35when exposed to the oxidizing atmosphere. The invention is believed tohave its greatest applicability to electronic component devicefabrication having widths less than 1 micron. Accordingly, theetching(s) to produce the FIG. 4 construction is ideally conducted tospace opposing linear outer lateral edges 42 and 44 less than 1 micronapart from one another. Accordingly in the illustrated preferredembodiment where a transistor is being fabricated in the preferredsub-micron fabrication, the illustrated first conductive layer 34 is atleast fabricated to have its opposing outer lateral edges spaced lessthan 1 micron apart. Such defines, in the illustrated cross-section, achannel length (i.e., minimum gate width) within channel region 40 ofsemiconductive substrate 32 of less than 1 micron.

[0027] Referring to FIG. 5, silicide layer 35 is etched at a faster ratethan any etching into edges 42 and 44 of layers 36 and 34 to recessouter lateral edges of silicide layer 35 to within outer lateral edgesof both layers 36 and 34 of the illustrated stack. Such producesconductive layers 34 and 35 within the illustrated cross-section to haverespective opposing outer lateral edges which are displaced from oneanother. Accordingly, the outer lateral edge of the layer with thehigher oxidation rate is recessed inwardly of corresponding outerlateral edges of the layers with lower oxidation rate in the particularoxidizing atmosphere.

[0028] The preferred etching is a wet etching, preferably with a basicsolution. An example is a solution comprising ammonium hydroxide andhydrogen peroxide, with a specific example solution being ammoniumhydroxide, H₂O₂, and H₂O in a mix of 0.25:1:5 by volume. Exampleconditions for such etching include ambient pressure, a temperatureranging from 40° C. to 70° C. for from 1 to 10 minutes. Alternate bases(i.e., KOH) could be used in addition to or instead of ammoniumhydroxide in the preferred basic wet etching. Such example chemistriescan provide substantially selective etching of layer 35 relative to theetching of layers 36, 34, and substrate 32 if it is exposed. In thecontext of this document, “substantially selective” is to be interpretedto mean an etch rate of one material relative to another of at least2:1.

[0029] Referring to FIG. 6, the substrate is exposed to the oxidizingatmosphere with a recessed edge of second layer 35 being exposed. In thepreferred embodiment, this is conducted to be effective to grow an oxidelayer 50 over outer lateral edges of silicide layer 35 and doped siliconlayer 34. Such is also effective to form oxide layer 50 over siliconsubstrate 32 and even, to perhaps a lesser degree, over insulating cap39. Thus, a recessed edge of layer 35 is oxidized. Preferably, layer 50is formed to produce oxide layer 50 to have opposing substantiallycontinuous straight linear outer lateral edges 52 at least over firstand second conductive materials 35 and 34 (i.e., over all conductivematerial of the gate stack within at least the one illustratedcross-section). Regardless and ideally, the prior art FIG. 2 outwardlateral bulges 25 do not occur. Oxide layer 50 ideally has a lateralthickness of less than 100 Angstroms and greater than 10 Angstroms overfirst conductive material 34. Further ideally in the application of theinvention to ever increasingly sub-micron devices, opposing linear outerlateral edges 52 of oxide layer 50 are formed to be less than 1 micronin separated distance. Alternate insulating material layers 50 couldalso of course be utilized.

[0030] After the preferred oxidizing to form oxide layer 50, a suitabledopant impurity is ion implanted into substrate 32 proximate gate stack38 to form one or more LDD regions, or halo regions, 60. Effectiveremoval or prevention of formation of lateral bulges 25 of the FIG. 2prior art can accordingly be utilized to position regions 60 moreproximate the outer lateral edges of the gate stack, particularly infabrication of sub-micron devices.

[0031] Referring to FIG. 7, insulative material is formed over oxidelayer 50 and is subsequently anisotropically etched to produceinsulative illustrated spacers 62. Subsequent ion implanting can then beconducted to provide dopant impurity into substrate 32 proximate thegate stack to form field effect transistor source/drain regions 64.

[0032] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method comprising: forming first andsecond layers over a substrate, the second layer having a higheroxidation rate than the first layer when exposed to an oxidizingatmosphere, the substrate having a periphery, the first layer having anexposed first outer edge spaced inside the substrate periphery, thesecond layer having an exposed first outer edge spaced inside thesubstrate periphery; etching into the second layer first edge at afaster rate than any etching into the first layer first edge and formingan exposed second outer edge of the second layer; and after the etching,exposing the substrate to the oxidizing atmosphere with the second layersecond outer edge exposed and forming an oxidized first layer edge. 2.The method of claim 1 comprising forming the second layer over the firstlayer.
 3. The method of claim 1 comprising forming the first layer overthe second layer.
 4. The method of claim 1 comprising forming the firstand second layers to be electrically conductive.
 5. The method of claim1 wherein the etching comprises wet etching.
 6. The method of claim 1wherein the etching comprises wet etching with a basic solution.
 7. Themethod of claim 1 wherein the etching comprises wet etching with asolution comprising ammonium hydroxide and hydrogen peroxide.
 8. Themethod of claim 1 further comprising forming a third layer over thefirst and second layers, the third layer having an exposed first outeredge spaced inside the substrate periphery, the third layer having alower oxidation rate than the oxidation rate of the second layer whenexposed to the oxidizing atmosphere, the etching into the second layerfirst edge forming the second layer second edge to be recessed inwardlyrelative to outer edges of both the first and third layers.
 9. Asemiconductor processing method comprising: forming a stack of at leasttwo conductive layers for an electronic component over a substrate, thetwo conductive layers having different oxidation rates when exposed toan oxidizing atmosphere, the layer with the higher oxidation rate havingan outer lateral edge which is recessed inwardly of a correspondingouter lateral edge of the layer with the lower oxidation rate; andexposing the stack of conductive layers to the oxidizing atmosphereeffective to grow an oxide layer over the outer lateral edges of thefirst and second layers.
 10. The method of claim 9 comprising formingthe higher oxidation rate layer over the lower oxidation rate layer. 11.The method of claim 9 comprising forming the lower oxidation rate layerover the higher oxidation rate layer.
 12. The method of claim 9comprising forming another layer over the at least two conductivelayers, the another layer having a lower oxidation rate than the layerhaving said higher oxidation rate when exposed to the oxidizingatmosphere, the outer lateral edge of the layer with said higheroxidation rate being recessed inwardly of a corresponding outer lateraledge of the another layer.
 13. The method of claim 12 wherein theanother layer is electrically insulative.
 14. The method of claim 9wherein one of the at least two conductive layers comprises conductivelydoped polysilicon and another of the at least two conductive layerscomprises a refractory metal silicide.
 15. A method of forming anelectronic component comprising: forming first and second conductivematerials over a substrate, the second material having a higheroxidation rate than an oxidation rate of the first material when exposedto an oxidizing atmosphere; first etching the first and secondconductive materials to form a conductive component, the conductivecomponent having opposing substantially continuous straight linear outerlateral edges of the first and second conductive materials; secondetching into the second material outer lateral edges to recess theminside of the first material outer lateral edges; and after the secondetching, exposing the substrate to the oxidizing atmosphere effective togrow an oxide layer over the outer lateral edges of the first and secondconductive materials.
 16. The method of claim 15 one of the first andsecond conductive materials comprises conductively doped polysilicon andthe other comprises a refractory metal silicide.
 17. The method of claim15 wherein the second etching comprises wet etching.
 18. The method ofclaim 15 wherein the first etching comprises dry etching and the secondetching comprises wet etching.
 19. The method of claim 15 wherein thesecond etching comprises wet etching with a basic solution.
 20. Themethod of claim 15 wherein the second etching comprises wet etching witha solution comprising ammonium hydroxide and hydrogen peroxide.
 21. Themethod of claim 15 comprising forming the second conductive material tobe received over the first conductive material.
 22. The method of claim15 wherein the first etching is conducted to space the opposing linearouter lateral edges less than 1 micron apart from one another.
 23. Themethod of claim 15 wherein the first etching is conducted to space theopposing linear outer lateral edges less than 1 micron apart from oneanother, and further comprising ion implanting into the substrateproximate outer lateral edges of the first and the second conductivematerials after the exposing.
 24. The method of claim 15 wherein thefirst etching is conducted to space the opposing linear outer lateraledges less than 1 micron apart from one another, the second etching andthe exposing being effective to form the oxide layer to have opposingsubstantially continuous straight linear outer lateral edges over thefirst and second conductive materials.
 25. The method of claim 24wherein the opposing linear outer lateral edges of the oxide layer areformed to be less than 1 micron apart.
 26. The method of claim 15comprising forming a third insulative material over the first and secondconductive materials, the first etching also etching the thirdinsulative material to form the conductive component to have aninsulative cap, the third insulative material having a lower oxidationrate than the second conductive material when exposed to the oxidizingatmosphere, the second etching recessing the second material outerlateral edges to within outer lateral edges of the third insulativematerial.
 27. The method of claim 26 wherein the first etching isconducted to form the insulative cap to have opposing outer lateraledges which are substantially straight continuously linear with theouter lateral edges of the first and second conductive materials, andthe first etching is conducted to space said opposing linear outerlateral edges less than 1 micron apart from one another.
 28. The methodof claim 26 wherein the first etching is conducted to form theinsulative cap to have opposing outer lateral edges which aresubstantially straight continuously linear with the outer lateral edgesof the first and second conductive materials, and the first etching isconducted to space the opposing linear outer lateral edges less than 1micron apart from one another, and further comprising ion implantinginto the substrate proximate outer lateral edges of the first and thesecond conductive materials after the exposing.
 29. The method of claim26 wherein the first etching is conducted to form the insulative cap tohave opposing outer lateral edges which are substantially straightcontinuously linear with the outer lateral edges of the first and secondconductive materials, and the first etching is conducted to space theopposing linear outer lateral edges less than 1 micron apart from oneanother, the second etching and the exposing being effective to form theoxide layer to have opposing substantially continuous straight linearouter lateral edges over the first and second conductive materials. 30.The method of claim 29 wherein the opposing linear outer lateral edgesof the oxide layer are formed to be less than 1 micron apart.
 31. Asemiconductor processing method of forming a transistor comprising:forming a gate dielectric layer, a doped silicon layer, a silicide layerand an insulating layer over a channel region of a substrate, thesilicide layer having a higher oxidation rate than oxidation rates ofthe doped silicon layer and the insulating layer when exposed to anoxidizing atmosphere; first etching the insulating layer, the silicidelayer and the doped silicon layer to form a conductive gate stack havingan insulating cap over the channel region, the gate stack having twoopposing and respectively linearly aligned outer lateral edges of theinsulating, silicide and doped silicon layers; second etching thesilicide layer substantially selectively relative to the insulating capand the doped silicon layer to recess outer lateral edges of thesilicide layer to within outer lateral edges of both the insulating anddoped silicon layers of the gate stack; after the second etching,exposing the substrate to the oxidizing atmosphere effective to grow anoxide layer over outer lateral edges of the silicide and doped siliconlayers; after the exposing, first implanting a dopant impurity into thesubstrate proximate the gate stack to form at least one of an LDD regionor a halo region; after the first implanting, forming insulativematerial over the oxide layer; and after forming the insulativematerial, second implanting a dopant impurity into the substrateproximate the gate stack to form transistor source/drain regions. 32.The method of claim 31 wherein the first etching is conducted to spacethe opposing substantially linear outer lateral edges less than 1 micronapart from one another.
 33. The method of claim 31 wherein the firstetching is conducted to space the opposing linear outer lateral edgesless than 1 micron apart from one another, the second etching and theexposing being effective to form the oxide layer to have opposingsubstantially continuous straight linear outer lateral edges over theinsulating, silicide and doped silicon layers.
 34. The method of claim33 wherein the opposing linear outer lateral edges of the oxide layerare formed to be less than 1 micron apart.
 35. The method of claim 31wherein the second etching comprises wet etching.
 36. The method ofclaim 31 wherein the first etching comprises dry etching and the secondetching comprises wet etching.
 37. The method of claim 31 wherein thesecond etching comprises wet etching with a basic solution.
 38. Themethod of claim 31 wherein the second etching comprises wet etching witha solution comprising ammonium hydroxide and hydrogen peroxide.
 39. Atransistor comprising: a semiconductive substrate; a stack of a gatedielectric layer over the semiconductive substrate, a first conductivelayer over the gate dielectric layer, a second conductive layerdifferent in composition from the first and received over the first, andan insulative cap over the second conductive layer; the first conductivelayer of the stack having opposing outer lateral edges which are spacedless than one micron apart defining a channel length within thesemiconductive substrate of less than one micron, the second conductivelayer of the gate stack having opposing outer lateral edges which arespaced apart less than the opposing outer lateral edges of the firstconductive layer are spaced apart; and an oxide layer formed over theouter lateral edges of the first conductive layer, the second conductivelayer and the insulative cap, the oxide layer having opposingsubstantially continuous straight linear outer lateral edges over theinsulating cap, the first conductive layer and the second conductivelayer.
 40. The transistor of claim 39 wherein the opposing linear outerlateral edges of the oxide layer are formed to be less than 1 micronapart.
 41. The transistor of claim 39 wherein the oxide layer has alateral thickness of less than 100 Angstroms over the first conductivelayer.
 42. The transistor of claim 39 wherein the oxide layer has alateral thickness of less than 100 Angstroms and greater than 10Angstroms over the first conductive layer.
 43. A transistor comprising:a semiconductive substrate; a gate stack formed over the semiconductivesubstrate and defining in at least one cross section a channel lengthwithin the semiconductive substrate of less than 1 micron, the gatestack comprising conductive material formed over a gate dielectriclayer; and an insulative layer formed on outer lateral edges of theconductive material, the insulative layer having opposing substantiallycontinuous straight linear outer lateral edges over all conductivematerial of the gate stack within the one cross section.
 44. Thetransistor of claim 43 wherein the opposing linear outer lateral edgesof the insulative layer are formed to be less than 1 micron apart. 45.The transistor of claim 43 wherein the insulative layer has a minimumlateral thickness of less than 100 Angstroms over said all conductivematerial.
 46. The transistor of claim 43 wherein the insulative layerhas a minimum lateral thickness of less than 100 Angstroms and greaterthan 10 Angstroms over said all conductive material.
 47. The transistorof claim 43 wherein the conductive material comprises at least twoconductive layers, the conductive layers within the one cross section ofthe gate stack having opposing outer lateral edges which are displacedfrom one another.